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Architecture
SuperNoVA_ Algorithm-Hardware Co-Design for Resource-Aware SLAM
  • 03/21
  • 18:45
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Using Analytical Performance/Power Model and Fine-Grained DVFS to Enhance AI Accelerator Energy Efficiency
  • 03/21
  • 17:37
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PiDRAM_A_Holistic_End-to-end_FPGA-based_Framework_for_Processing-in-DRAM
  • 03/03
  • 13:55
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MPU-Sim_ A Simulator for In-DRAM Near-Bank Processing Architectures
  • 03/03
  • 10:32
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In-Memory Data Parallel Processor
  • 02/26
  • 14:04
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Multi-Layer In-Memory Processing
  • 02/26
  • 14:01
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pSyncPIM_ Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures
  • 02/26
  • 13:58
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Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation
  • 02/26
  • 13:55
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PIMnet_A_Domain-Specific_Network_for_Efficient_Collective_Communication_in_Scalable_PIM
  • 02/26
  • 13:54
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ROC_DRAM-based_Processing_with_Reduced_Operation_Cycles
  • 02/26
  • 13:50
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