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Architecture
Characterizing Cloud-Native LLM Inference at ByteDance and Exposing Optimization Challenges and Opportunities for Future AI Accelerators
  • 05/12
  • 11:52
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Cambricon-CIM_ Enabling Energy-Efficient and Error-Resilient Analog CIM Acceleration via Reformation of Coding Bases
  • 05/11
  • 22:36
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BARD_ Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism
  • 05/11
  • 21:35
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Athena_Synergizing_Data_Prefetching_and_Off-Chip_Prediction_via_Online_Reinforcement_Learning
  • 05/11
  • 17:52
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ASPA_ Reassigning DDR5 Parity Bandwidth
  • 05/11
  • 17:16
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Area Bloating and the Future of Specialization
  • 05/11
  • 15:46
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AQPIM_ Breaking the PIM Capacity Wall for LLMs with In-Memory Activation Quantization
  • 05/11
  • 14:43
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Adaptive Draft Sequence Length_ Enhancing Speculative Decoding Throughput on PIM-Enabled Systems
  • 05/11
  • 14:27
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A Deadlock-Free Bridge Module for Inter-Chiplet Cache-Coherent Communication in an Open Chiplet Ecosystem
  • 05/09
  • 17:53
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Accelerating Retrieval-Augmented Generation
  • 04/29
  • 11:21
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